Global and local clock distribution networks for multiprocessor systems

Abstract

A dual-rail buffer circuit is utilized to construct a modular global clock distribution network. The dual-rail buffer circuit includes first and second input ports, and first and second output ports coupled via respective first and second channels to the first and second input ports. The dual-rail buffer circuit includes two inverters on the first channel and two inverters on the second channel. The dual-rail buffer circuit also includes two fractional feed-forward equalizers that cross-connect between the two channels. A global clock distribution network includes a plurality of standardized units and T connections configured in a tree structure, where each standardized unit includes the dual-rail buffer circuit coupled to a transmission line. The modular global clock distribution network provides synchronized timing information to a plurality of circuit modules. The length of the standardized units is determined from a pitch length of the circuit modules.