Integrated circuit margin measurement for the detection of rare events

Abstract

A specific logic circuitry of a semiconductor Integrated Circuit (IC) is measured by a sensor. The sensor includes: a signal splitter that splits a signal from the specific logic circuitry into two test paths; a delay element that receives and applies a delay to a first test path, the delay based on a predetermined timing margin that is selected from a group of discrete timing margin values comprising a shortest timing margin value and at least one longer timing margin value; a comparison circuit that compares the delayed first test path and a second test path and provides a measurement output according to the comparison for an instance of measuring; and a controller that sets the predetermined timing margin such that, over the instances of measuring, a frequency of selection of the shortest timing margin value is higher than a frequency of selection of each longer timing margin value.