The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2026
Filed:
Sep. 11, 2023
Applicant:
Christos Tsironis, St-Laurent, CA;
Inventor:
Christos Tsironis, Kirkland, CA;
Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 1/04 (2006.01); G01R 1/067 (2006.01); G01R 27/32 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2822 (2013.01); G01R 1/0416 (2013.01); G01R 1/06772 (2013.01); G01R 27/32 (2013.01);
Abstract
Planarity adjustment of RF microprobes in a load pull setup on wafer, using a low-profile impedance tuner that is mounted on a 3-axis tuner positioner under an angle matching the angle of the wafer probe is performed using a separation of the tuning module from the tuner housing and allowing it to rotate around an axis through the tips of the wafer microprobe. This renders the directly connected tuner autonomous and compatible with all existing probe stations.
Tsironis, Christos. (2026). Load pull tuner with integrated on-wafer planarity control (U.S. Patent No. 12768876). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12768876
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile