The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

Jul. 23, 2024
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Roman Ogirko, Lviv, UA;

Edward Gerard O'malley, Claremorris, IE;

Cathal O'lionaird, Cork, IE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); G01R 19/165 (2006.01);
U.S. Cl.
CPC ...
G01R 19/16528 (2013.01); G01R 19/16504 (2013.01);
Abstract

An overload detector circuit includes first logic circuitry and second logic circuitry. The first logic circuitry to receive a bitstream from a sigma-delta modulator (SDM) of a receiver channel, the first logic circuitry to compare a current bit of the bitstream with a previous bit of the bitstream and output an indication of as match. The second logic circuitry to track a number of consecutive matches in the bitstream and output an indication of a first overload condition responsive to the number of consecutive matches satisfying a first threshold criterion.


Find Patent Forward Citations

Ogirko, Roman. (2026). Sigma-delta modulator (sdm) overload detector circuit (U.S. Patent No. 12768868). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12768868

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…