Multi-chip integrated circuit devices having recessed regions therein that support high yield dicing

Abstract

An integrated circuit device includes a semiconductor substrate having a first device region, a second device region, and a scribe line region therein. The scribe line region, which extends between the first and second device regions, includes a first edge region adjacent the first device region, a second edge region adjacent the second device region and a cutting region extending between the first and second device regions. A lower interlayer insulating layer is provided on the first and second device regions and on the scribe line region. A first multi-level guard ring is provided, which at least partially surrounds the first device region, when viewed from a plan perspective. An insulating structure is provided, which has a recess therein. The recess extends adjacent the first multi-level guard rings and exposes an upper surface of the lower interlayer insulating layer.