Three-dimensional memory device and enhanced electronic system

Abstract

The present disclosure provides for apparatuses and systems including integrated circuit devices. In some embodiments, an integrated circuit device includes a semiconductor substrate including a memory cell area and a connection area, a gate stack including a plurality of word line gate layers and a plurality of insulating layers and having a step structure in the connection area, a word line cut region passing through the plurality of word line gate layers in the memory cell area and the connection area and extending in a third direction, a plurality of first channel structures disposed on the memory cell area, a string select line gate layer disposed on the gate stack in the memory cell area, a plurality of second channel structures passing through the string select line gate layer, and a string select line cut region passing through the string select line gate layer.