The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2026

Filed:

Sep. 09, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Keisuke Nakatsuka, Kobe Hyogo, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); H10W 80/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); H10W 90/00 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 90/792 (2026.01);
Abstract

A semiconductor memory device according to an embodiment includes a substrate, a first conductor layer, second conductor layers, a first semiconductor layer, a pillar, and a contact. The pillar has a portion provided to penetrate the second conductor layers and the first semiconductor layer. The contact is electrically connected to the pillar and the first conductor layer. The pillar includes a second semiconductor layer, a first insulator layer provided at least between the second semiconductor layer and the second conductor layers, and a third semiconductor layer provided between the second semiconductor layer and the first semiconductor layer and in contact with each of the second semiconductor layer and the first semiconductor layer.


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Nakatsuka, Keisuke. (2026). Semiconductor memory device (U.S. Patent No. 12764954). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12764954

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