The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2026

Filed:

Aug. 12, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jin Young Park, Suwon-si, KR;

Hyuk Kim, Seongnam-si, KR;

Yeon Geun Yook, Seongnam-si, KR;

Young Sik Lee, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10W 20/42 (2026.01); H10W 20/435 (2026.01);
Abstract

Semiconductor memory devices may include a cell substrate including a cell array region, first and second extension regions and a through region, a first mold structure including first gate electrodes stacked in a stepwise manner, a first interlayer insulating layer extending conformally on the first gate electrodes on the second extension region, a second interlayer insulating layer on the first interlayer insulating layer, a second mold structure including second gate electrodes on the second interlayer insulating layer and stacked on the first extension region in the stepwise manner, a channel structure in the first and second mold structures on the cell array region, a first cell contact structure in the first mold structure on the second extension region, and a second cell contact structure in the first and second mold structures on the first extension region. The first and second interlayer insulating layers may have different impurity concentrations.


Find Patent Forward Citations

Park, Jin. (2026). Semiconductor memory devices, electronic systems including the same and fabricating methods of the same (U.S. Patent No. 12764953). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12764953

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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