Semiconductor memory device including gate insulating pattern including high-k dielectric material

Abstract

A semiconductor memory device includes a bit line, first and second word lines spaced apart from each other on the bit line, a back gate electrode between the first and second word lines, a first active pattern between the first word line and the back gate electrode, a second active pattern between the second word line and the back gate electrode, contact patterns connected to the first and second active patterns, respectively, and a first gate insulating pattern between the first active pattern and the first word line and between the second active pattern and the second word line. A top surface of the first gate insulating pattern is located at substantially a same height as top surfaces of the first and second word lines. The first gate insulating pattern includes a high-k dielectric material.