The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2026

Filed:

Feb. 26, 2025
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Daniel Domes, Werl, DE;

Richard Kuchcinski, Warstein, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/082 (2006.01);
U.S. Cl.
CPC ...
H03K 17/0822 (2013.01);
Abstract

A circuit includes an input node configured to receive a gate control signal for controlling a dual gate transistor arrangement, a first output node configured to be coupled to a first gate node of the dual gate transistor arrangement, a first switch coupled between the input node and the first output node, and a second output node configured to be coupled to a second gate node of the dual gate transistor arrangement and coupled to the input node. A control circuit is configured to, upon detecting that the gate control signal indicates a turn-off of the dual gate transistor arrangement, open the first switch for a first predefined time period, and close the first switch after the first predefined time period.


Find Patent Forward Citations

Domes, Daniel. (2026). Circuit, system and method related to a dual gate transistor arrangement (U.S. Patent No. 12763765). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12763765

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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