Memory device and test method for the memory device

Abstract

A memory device comprising a memory core including a memory cell array including a plurality of memory cells, the memory cell array being divided into a plurality of memory banks, a Built-In Self Test (BIST) circuit configured to select a target memory bank from the plurality of memory banks and perform a parallel test on the target memory bank, and a control circuit configured to control the parallel test. The BIST circuit may determine at least one defective memory cell outputting a defective bit among target memory cells included in the target memory bank, and may determine whether the defective memory cell is a single defective memory cell or an adjacent double defective memory cell, and the control circuit May determine the target memory bank to be a defective memory bank when the defective memory cell is not the single defective memory cell and the adjacent double defective memory cell.