Memory programming schemes with adjustable verification voltages for reducing data retention loss

Abstract

An apparatus for data storage includes circuitry and a plurality of memory cells. The memory cells are coupled to word lines (WLs), and are configured to store data values in respective predefined programming levels. The circuitry is configured to: receive data values for storage in the memory cells of a given WL, select memory cells of the given WL that are to store a given data value among the received data values, set a verification voltage for programming the selected memory cells, so that a difference between the verification voltage and a read voltage predetermined for the selected memory cells depends on a rate of drift that is expected to occur to a threshold voltage distribution associated with the selected memory cells when programmed, apply one or more programming pulses to the given WL, and verify that the selected memory cells have been programmed successfully using the set verification voltage.