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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12763111 B1

PDFFull Text
Date of Patent:
Oct. 13, 2026

Filed:

May. 22, 2024

Logic die-based techniques for dram row segmentation and fine-grained accesses on stacked memory

Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Vignesh Adhinarayanan, Austin, TX (US);

Hyung-Dong Lee, Austin, TX (US);

Bradford Beckmann, Bellevue, WA (US);

Seyedmohammad Seyedzadehdelcheh, Bellevue, WA (US);

Sergey Blagodurov, Bellevue, WA (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:

Patterson + Sheridan, LLP

Primary Examiner:

Viet Q Nguyen

Int. Cl.
CPC ...
G11C 5/02 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01); H10B 80/00 (2023.01); H10W 90/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
G11C 5/02 (2013.01); G11C 11/4085 (2013.01); G11C 11/4087 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); H10B 80/00 (2023.02); H10W 90/00 (2026.01); H10W 90/297 (2026.01); H10W 90/792 (2026.01);
Abstract

Integrated circuit (IC) memory devices and methods for fabricating the same are provided. In one example, an integrated circuit (IC) memory device is provided that includes a substrate, at least two or more memory (IC) dies, and a non-memory IC die integrated in a chip package. The memory (IC) dies are stacked on the substrate to form a memory die stack. The non-memory IC die contains row segmentation logic having an output routed to corresponding wordline drivers of the memory IC dies through vertical wiring passing through the memory die stack.

Find Patent Forward Citations

Adhinarayanan, Vignesh. (2026). Logic die-based techniques for dram row segmentation and fine-grained accesses on stacked memory (U.S. Patent No. 12763111). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12763111

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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