Display configuration for refresh rate control

Abstract

A display device includes a plurality of image-forming elements arranged in a grid, including a plurality of rows and columns. A gate integrated circuit (IC) outputs a clock signal. A gate output buffer controls whether the clock signal is received by image-forming elements in a corresponding one or more rows. A source IC outputs data signals to control the plurality of image-forming elements. A block selection component controls, via a block selection signal, whether image-forming elements in a corresponding one or more columns are refreshed based at least in part on the data signals. A timing controller controls the output enable signal and the block selection signal to thereby control refresh rates for the plurality of image-forming elements, such that a first display region is refreshed at a first refresh rate, and a second display region is refreshed at a second refresh rate.