Apparatus and methods for generation of an intermediate representation for artificial intelligence centric architectures

Abstract

A compiler compiles, for example, a deep learning (DL) model for artificial intelligence (AI) centric architectures, generating a control graph intermediate representation (IR). The IR denotes compute nodes and control nodes, and edges denote the control flow between the nodes. A compute node, represented by a circle on the graph, encapsulates a computation (e.g., operation) to be executed on a compute (e.g., accelerator) device. A control node, represented by a diamond on the graph, encapsulates the logic to decide on the next compute node to execute (e.g., in case of conditional execution) and to enqueue job requests into an input queue of a compute device to execute that compute node. As execution may occur on different compute devices, the compiler is configured to operate without assuming a shared memory address space between different compute devices, making no assumption of a single program counter.