Flexible architecture for floating-point and integer compute-in-memory

Abstract

The disclosure describes systems and methods for mixed-mode, mixed-precision computation using a configurable compute engine for vector-matrix operations. A processing system selects a floating-point mode or an integer mode, selects a precision, and gates inactive datapath portions to reduce energy and stabilize latency. Streaming and stationary operand registers supply compute circuitry that, in floating-point mode, forms a mantissa product and product exponent, combines signs, and aligns the product using a power-of-two generator that drives a selection network based on the exponent. In integer mode, the same selection network performs integer multiplication from bitwise inputs, with sign handling applying two's-complement correction prior to accumulation. Parallel adder trees feed a hierarchical output accumulator sized to the selected precision, and normalization performs leading-one detection, mode-dependent exponent correction, rounding, and zero flushing. Optional dequantization folds scale tensors into the exponent path, and implementations support compute-in-memory or conventional accelerators.