Power timing control device and method

Abstract

Power timing control devices and methods are disclosed. Each of one or more controlled chips is enabled based on a logical-AND-gated operation of primary and auxiliary enable signals to generate a control voltage based on a DC power voltage. In a signal timing sequence, a representative moment during the control voltage falling from high to low level occurs earlier than a moment when a level on a signal waveform of the DC power voltage falling from high to low level equals a minimum operation voltage level for the controlled chip. In this way, a power timing control operation can be performed under both light and heavy load conditions of a system, and a controller can be driven for powering up and off the system according to the control voltage, thereby effectively preventing the controller from abnormality or breakdown.