The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

May. 15, 2023
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Mingyi Yu, Saratoga, CA (US);

Gregory Patrick Bodi, Santa Cruz, CA (US);

Gabriele Gorla, Santa Clara, CA (US);

Xiang Sun, Los Gatos, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 3/46 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H05K 1/115 (2013.01); H05K 3/4644 (2013.01); H05K 1/0251 (2013.01); H05K 2201/09509 (2013.01); H05K 2201/09536 (2013.01); H05K 2201/096 (2013.01); H05K 2203/1476 (2013.01);
Abstract

A printed circuit board (PCB) includes an exterior section having a first set of layers including an outermost conductive layer. The PB further includes an interior section, adjacent to the exterior section, having a second set of layers including a first conductive layer corresponding to a first end of the interior section, a second conductive layer corresponding to a second end of the interior section opposite the first end, and a third conductive layer disposed between the first conductive layer and the second conductive layer. The exterior section further includes a set of vias extending from an outermost conductive layer to the first conductive layer. The interior section further includes a buried skip via extending from the first conductive layer to the third conductive layer.


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