Double-data rate transmission within a system-on-chip via network-on-chip interconnects

Abstract

Double-data rate (DDR) transmission within a system-on-chip (SoC) via network-on-chip (NOC) interconnects is described. A method for transmitting data includes a local programmable delay circuit receiving a source synchronous clock (SSC) signal and outputting a delayed source synchronous clock (SSC) signal. The method further includes a local pulse generator, associated with a first NOC interconnect stage, receiving the delayed SSC signal and generating a first pulse in response to a first phase of the delayed SSC signal and generating a second pulse in response to a second phase of the delayed SSC signal. The method further includes a flop-repeater circuit, associated with the first NOC interconnect stage, capturing and launching data received from the source circuit in response to each of the first pulse and the second pulse. The method further includes a local offset circuit receiving the delayed SSC signal and providing a de-skewed SSC signal.