The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

Sep. 25, 2024
Applicant:

Intelligent Memory Limited, Kwai Chung, HK;

Inventor:

Peter Poechmueller, Jinan, CN;

Assignee:

Intelligent Memory Limited, Kwai Chung, HK;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/56 (2006.01);
U.S. Cl.
CPC ...
G11C 29/56012 (2013.01); G11C 29/56016 (2013.01); G11C 2029/5602 (2013.01);
Abstract

A motherboard assembly for testing memory components is described. The motherboard assembly has at least one CPU communicatively coupled with at least one memory channel, and a memory controller or BIOS programmed to continue booting in the presence of memory component failures. The memory controller or BIOS skips read/write training procedures when a failure is detected, and uses preset values for PHY registers from a previous successful booting procedure to continue the current booting without powering off. The memory controller or BIOS is also programmed to provide adjustable retention settings and adjustable speed settings without rebooting or powering off.


Find Patent Forward Citations

Poechmueller, Peter. (2026). Motherboard for testing memory modules in the presence of failures (U.S. Patent No. 12755810). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12755810

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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