The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

Nov. 05, 2024
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventors:

Hsuan Liang, Zhudong Township, TW;

Steve Nagel, Chandler, AZ (US);

Chu-Kuang Tsai, New Taipei City, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01);
U.S. Cl.
CPC ...
G11C 16/102 (2013.01); G11C 16/0433 (2013.01); G11C 16/14 (2013.01);
Abstract

EEPPROM array having memory cells arranged in rows and columns, wherein the memory cells have a select transistor and a sense transistor; memory sections include a plurality of memory cells and a section select transistor; a source line physically coupled to a source terminal of a section select transistor; a wordline physically coupled to a gate of a section select transistor and a gate of a select transistor; and a sense gate line physically coupled to a gate of a sense transistor. An erase operation may be done by applying: a low voltage to the source line; a high voltage to the sense gate line; and a middle voltage to the wordline.


Find Patent Forward Citations

Liang, Hsuan. (2026). Memory array and methods of operation (U.S. Patent No. 12755793). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12755793

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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