The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2026
Filed:
Jun. 30, 2023
Xilinx, Inc., San Jose, CA (US);
Chia-Jui Hsu, Santa Clara, CA (US);
Fnu Sindhoori, Milpitas, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Compiling a tensor specification for multi-dimensional direct memory access circuit configurations includes generating a first list of tile combination objects from a tensor tiling specification. The first list specifies a sequence of tiles specified by the tensor tiling specification in which each tile object represents a single tile of a tensor data structure. A second list of tile combination objects is generated by combining selected ones of the tile combination objects from the first list. Each tile combination object of the second list represents one or more tile objects. The tile combination objects of the second list are converted into buffer descriptor objects that include buffer descriptor parameters. Each of the buffer descriptor objects that is non-compliant with hardware constraints corresponding to a data mover circuit that is configurable using the buffer descriptor objects is legalized. The buffer descriptor objects are output, as legalized.
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