Memory device, memory controller, and storage device including the same

Abstract

A memory device includes a memory cell array including a first memory region storing first data, a page buffer including a first latch configured to store data dumped from the memory cell array, and a control logic circuit configured to receive parity adjustment information from an external device and control an operation of the memory cell array. The first data includes first user data and first parity data including parity bits generated based on the first user data, and the control logic circuit dumps first parity data of which a size is adjusted based on the parity adjustment information to the first latch.