The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2026
Filed:
Dec. 12, 2022
Applicant:
Lawrence Semiconductor Research Laboratory, Inc., Tempe, AZ (US);
Inventors:
Assignee:
Lawrence Semiconductor Research Laboratory, Inc., Tempe, AZ (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B81B 3/00 (2006.01); B81C 1/00 (2006.01);
U.S. Cl.
CPC ...
B81B 3/0021 (2013.01); B81C 1/00595 (2013.01); B81B 2203/0118 (2013.01); B81B 2203/0127 (2013.01);
Abstract
An engineered substrate comprises a base substrate, a monocrystalline sacrificial intermediate layer epitaxially grown over the base substrate, and a monocrystalline top layer epitaxially grown over the monocrystalline sacrificial intermediate layer. The engineered substrate may be used to form a free-standing microstructure comprising the engineered substrate by removing at least a portion of the intermediate layer from between the base substrate and the top layer.
Arena, Chantal. (2026). Engineered substrates, free-standing semiconductor microstructures, and related systems and methods (U.S. Patent No. 12753068). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12753068
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile