The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2026

Filed:

Sep. 19, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Eunsu Lee, Suwon-si, KR;

Jongbo Shim, Suwon-si, KR;

Sungeun Pyo, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H10W 90/00 (2026.01); H10B 80/00 (2023.01); H10W 72/30 (2026.01); H10W 74/15 (2026.01); H10W 80/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10B 80/00 (2023.02); H10W 72/387 (2026.01); H10W 74/15 (2026.01); H10W 80/721 (2026.01); H10W 90/297 (2026.01); H10W 90/722 (2026.01); H10W 90/732 (2026.01);
Abstract

A semiconductor device includes a first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a first active layer adjacent to the first surface, the first semiconductor substrate having a quadrangle shape from a plan view; a first through electrode penetrating at least a portion of the first semiconductor substrate and connected to the first active layer; a second chip connection pad on the second surface of the first semiconductor substrate and connected to the first through electrode; a first dummy pattern positioned outside the second chip connection pad on the second surface of the first semiconductor substrate from the plan view, the first dummy pattern comprising a line pattern extending horizontally along the second surface of the first semiconductor substrate; and a first chip connection pad on the first surface of the first semiconductor substrate and connected to the first through electrode. The first dummy pattern is disposed adjacent to at least one side of four sides of the quadrangle shape of the first semiconductor substrate from the plan view.


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