The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2026

Filed:

Oct. 24, 2023
Applicant:

Taipei Anjet Corporation, Taipei City, TW;

Inventors:

Nobuo Machida, Kyoto, JP;

Wen-Chin Wu, Taipei City, TW;

Assignee:

Taipei ANJET Corporation, Taipei City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/66 (2025.01); H10D 30/01 (2025.01); H10D 30/65 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 30/668 (2025.01); H10D 30/0295 (2025.01); H10D 30/0297 (2025.01); H10D 30/658 (2025.01); H10D 64/513 (2025.01);
Abstract

A 3D trenched MOSFET device includes a semiconductor substrate, an epitaxial layer, an epitaxial layer, a doped area, first doped wells, second doped wells, a trenched gate, first heavily-doped areas, a patterned insulation layer, and a conduction layer. The epitaxial layer is formed on the semiconductor substrate. The doped area, the first doped wells, and the second doped wells are formed in the epitaxial layer. The trenched gate, formed in the epitaxial layer and the first doped wells, penetrates through the doped area and surrounds the second doped wells. The bottoms of the first doped wells and the second doped wells are lower than the bottom of the trenched gate. The first heavily-doped areas are formed in the doped area. The first heavily-doped areas respectively surround the second doped wells and the trenched gate surrounds the first heavily-doped areas.


Find Patent Forward Citations

Machida, Nobuo. (2026). Three-dimensional (3d) trenched metal-oxide-semiconductor field-effect transistor (mosfet) device including first doped wells and second doped wells and method for fabricating the same (U.S. Patent No. 12751043). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12751043

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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