Semiconductor device comprising trench gate along with separation layers

Abstract

A semiconductor device including a word line intersecting and overlapping an active region and extending in a first direction, a word line capping layer on the word line, bit lines interacting and overlapping the active region and extending in a second direction, buried contacts each connected to the active region, direct contacts each connecting the active region to a corresponding one of the bit lines, a fence pattern on top of the word line capping layer, and a landing pad connected to a corresponding one of the buried contacts, wherein the fence pattern is within a fence pattern trench at a corresponding space between a corresponding pair the bit lines and between a corresponding pair the buried contacts, the fence pattern includes a first fence pattern and a second fence pattern on the first fence pattern that include different materials from each other may be provided.