The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2026

Filed:

Jun. 24, 2024
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Jagadeesh Anathahalli Singrigowda, Bangalore, IN;

Rajesh Mangalore Anand, Bangalore, IN;

Shreevatsa M, Bangalore, IN;

Girish A S, Bangalore, IN;

Prasant Kumar Vallur, Bangalore, IN;

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
H03K 17/6874 (2013.01); H03K 17/6872 (2013.01);
Abstract

A circuit includes a first and second PMOS transistor serially coupled between a high voltage power supply and a pad, a gate of the first PMOS transistor coupled to a first signal from an internal circuit, the first signal configured to switch between a first voltage and the high voltage power supply, a gate and drain of the second PMOS transistor connected to an adaptive control node and the pad, respectively, and a first and second NMOS transistor serially coupled between the pad and a ground, a gate of the first NMOS transistor coupled to a second signal from the internal circuit, the second signal configured to switch between a second voltage and the ground, a gate and drain of the second NMOS transistor connected to the adaptive control node and the pad, respectively, wherein the adaptive control node is configured to switch between the first and second voltage.


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