Clock transmission circuit and semiconductor device including the same

Abstract

A clock transmission circuit comprising a first inverter configured to invert an input clock signal received through a clock input terminal to generate an inverted clock signal, and output the inverted clock signal to a clock output terminal, a feedback impedance circuit connected in parallel with the first inverter between the clock output terminal and the clock input terminal, and an inverter chain unit having a smaller size than the first inverter, including an odd number of second inverters connected in a chain form, connected to the clock output terminal, and configured to invert the inverted clock signal to generate an output clock signal and output the output clock signal to the clock output terminal.