The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2026

Filed:

May. 31, 2019
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Vadym Kliuchnikov, Redmond, WA (US);

Nicolas Delfosse, Seattle, WA (US);

Alexander Vaschillo, Redmond, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 10/00 (2022.01); G06F 30/392 (2020.01); G06N 10/20 (2022.01); G06N 10/40 (2022.01); G06N 10/70 (2022.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06N 10/20 (2022.01); G06N 10/40 (2022.01); G06N 10/70 (2022.01); H03K 19/20 (2013.01);
Abstract

Disclosed herein are example layouts and layout generation techniques for fault-tolerant quantum computers. Example embodiments comprise methods for performing a layout reduction technique for fault-tolerant quantum computing. In certain embodiments, a layout of an arbitrary quantum circuit is reduced to a layout of exponents of a multiple qubit Pauli matrix and measurements of a multiple qubit Pauli matrix. In certain embodiments, qubits are marked as one of a data, interface, or ancilla qubit for a 2D nearest neighbor graph of qubit connectivity, and an ancilla-path is provided from a respective data qubit to a respective interface qubit.


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