Semiconductor package and method of manufacturing the semiconductor package

Abstract

A semiconductor package includes a first redistribution wiring layer having first and second surfaces opposite to each other, the first redistribution wiring layer including a plurality of first redistribution wires and a plurality of landing pads electrically connected to the first redistribution wires, the plurality of landing pads exposed from the second surface, a second redistribution wiring layer disposed on the first surface of the first redistribution wiring layer, the second redistribution wiring layer including an insulating layer, a logic semiconductor chip provided in the insulating layer, second redistribution wires electrically connected to the logic semiconductor chip, and third redistribution wires electrically connected to the first redistribution wires, the third redistribution wires extending to penetrate the insulating layer, a third redistribution wiring layer disposed on the second redistribution wiring layer, the third redistribution wiring layer including fourth redistribution wires electrically connected to the third redistribution wires, and a semiconductor substrate disposed on an upper surface of the third redistribution wire layer, the semiconductor substrate including at least one memory semiconductor chip electrically connected to the fourth redistribution wires.