The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Mar. 07, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jaewon Choi, Suwon-si, KR;

Jongbo Shim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/05 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 70/69 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 70/093 (2026.01); H10W 70/05 (2026.01); H10W 70/095 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 70/69 (2026.01); H10W 90/00 (2026.01); H10W 90/701 (2026.01); H10W 72/07232 (2026.01); H10W 74/15 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract

A method of manufacturing a semiconductor package includes; positioning a passive element on an upper insulating layer of a package substrate, wherein the upper insulating layer of the package substrate exposes upper surfaces of first substrate pads and second substrate pads, the passive element includes; electrodes on respective corners of a lower surface of the passive element, solder members respectively on the electrodes, and an insulating spacer on a central portion of the lower surface of the passive element between the solder members, and the solder members are respectively disposed on the second substrate pads. The method further includes; bonding the passive element on the package substrate through the solder members and the second substrate pads, and bonding a semiconductor device to the first substrate pads on the package substrate through conductive bumps on a lower surface of the semiconductor device, wherein the semiconductor device is laterally spaced apart from the passive element on the package substrate.


Find Patent Forward Citations

Loading…