The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Jun. 09, 2021
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Shotaro Yamamoto, Tokyo, JP;

Yoshiko Tamada, Tokyo, JP;

Kazuya Okada, Tokyo, JP;

Seiji Oka, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 40/25 (2026.01); H10W 70/40 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 40/255 (2026.01); H10W 70/415 (2026.01); H10W 90/00 (2026.01); H10W 90/811 (2026.01); H10W 90/753 (2026.01); H10W 90/755 (2026.01); H10W 90/792 (2026.01); H10W 90/794 (2026.01);
Abstract

A semiconductor module includes a semiconductor chip, an insulating substrate, a relay board, and a heat-dissipating component. The insulating substrate includes a main circuit pattern and an insulating layer. The main circuit pattern is electrically connected to the semiconductor chip. The relay board sandwiches the semiconductor chip together with the main circuit pattern in a direction in which the insulating layer and the semiconductor chip sandwich the main circuit pattern. The relay board is electrically connected to the main circuit pattern through the semiconductor chip. The heat-dissipating component is sandwiched between the insulating substrate and the relay board in the sandwiching direction. The main circuit pattern at least partially surrounds the heat-dissipating component on the insulating layer.


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