The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Mar. 11, 2024
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Takafumi Masuda, Kawasaki, JP;

Mutsumi Okajima, Yokkaichi, JP;

Nobuyoshi Saito, Ota, JP;

Keiji Ikeda, Kawasaki, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/41 (2026.01); H10B 12/00 (2023.01); H10W 20/42 (2026.01); H10W 20/43 (2026.01);
U.S. Cl.
CPC ...
H10W 20/435 (2026.01); H10B 12/315 (2023.02); H10B 12/482 (2023.02); H10W 20/42 (2026.01); H10W 20/43 (2026.01);
Abstract

A semiconductor memory device includes a memory layer and a via-wiring extending in a first direction. The memory layer includes a semiconductor layer electrically connected to the via-wiring, a gate electrode including parts opposed to surfaces of the semiconductor layer on one side and the other side in the first direction, a memory portion disposed on one side in a second direction with respect to the semiconductor layer, and a wiring disposed on the other side in the second direction with respect to the semiconductor layer. In a cross-sectional surface perpendicular to the first direction and including one of the parts of the gate electrode, the via-wiring includes a surface opposed to the gate electrode and a surface not opposed to the gate electrode. A part of the gate electrode is disposed on a memory portion side with respect to the via-wiring in the second direction.


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