The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2026
Filed:
Jan. 09, 2024
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Tzu-Ging Lin, Kaohsiung City, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
A method includes forming a plurality of semiconductor regions, forming a plurality of gate stacks, wherein the plurality of gate stacks are on first portions of the plurality of semiconductor regions, and etching the plurality of gate stacks to form a plurality of openings in the plurality of gate stacks. The plurality of openings include a first opening in a first gate stack, and a second opening in a second gate stack. The first opening and the second opening are immediately neighboring each other and have an overlap with an overlap distance equal to or greater than a pitch of the plurality of semiconductor regions. The plurality of semiconductor regions are etched to extend the plurality of openings downwardly to be between dielectric isolation regions, followed by filling the plurality of openings to form fin isolation regions. The gate isolation regions are spaced apart from the fin isolation regions.