The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Nov. 13, 2023
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Seunghyun Lee, Yongin-si, KR;

Sewan Son, Yongin-si, KR;

Sungho Kim, Yongin-si, KR;

Minwoo Woo, Yongin-si, KR;

Kwanhee Lee, Yongin-si, KR;

Jiseon Lee, Yongin-si, KR;

Kyeongwoo Jang, Yongin-si, KR;

Sugwoo Jung, Yongin-si, KR;

Assignee:

Samsung Display Co., Ltd., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10K 59/122 (2023.01); H10K 59/131 (2023.01);
U.S. Cl.
CPC ...
H10K 59/122 (2023.02); H10K 59/131 (2023.02);
Abstract

A display apparatus includes a substrate including a display area and a non-display area outside the display area, a pixel circuit layer disposed on the substrate and including at least one transistor, a first sub-pixel electrode, a second sub-pixel electrode, and a third sub-pixel electrode spaced apart from each other and disposed on the pixel circuit layer, a first conductive bank layer disposed on the first sub-pixel electrode and including a first opening overlapping the first sub-pixel electrode, a second conductive bank layer disposed on the second sub-pixel electrode and including a second opening overlapping the second sub-pixel electrode, and a third conductive bank layer disposed on the third sub-pixel electrode and including a third opening overlapping the third sub-pixel electrode, wherein the first conductive bank layer, the second conductive bank layer, and the third conductive bank layer are spaced apart from each other.


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