The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Apr. 12, 2023
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Tinghua Shang, Beijing, CN;

Yi Zhang, Beijing, CN;

Haigang Qing, Beijing, CN;

Biao Liu, Beijing, CN;

Bangqing Xiao, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10K 59/121 (2023.01); H10K 59/131 (2023.01);
U.S. Cl.
CPC ...
H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/131 (2023.02);
Abstract

An array substrate includes a plurality of pixel driving circuits, and each pixel driving circuit at least includes a compensation transistor. The array substrate includes a substrate, an active layer, a first gate layer and a second gate layer. The active layer includes an active layer pattern of the compensation transistor, which includes two channel areas and a conductive area therebetween. The first gate layer includes a first gate signal line, and an orthographic projection of the first gate signal line on the substrate is overlapped with orthographic projections of the two channel areas on the substrate. The second gate layer includes a voltage stabilization pattern, which is configured to receive a power supply voltage signal, and an orthographic projection of the voltage stabilization pattern on the substrate is overlapped with an orthographic projection of the conductive area on the substrate.


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