The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Aug. 25, 2023
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Nobuaki Okada, Kawasaki, JP;

Akihiko Chiba, Yokohama, JP;

Kenichi Matoba, Yokohama, JP;

Haruna Sugiura, Kawasaki, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 80/00 (2026.01); H01L 25/065 (2023.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10B 80/00 (2023.02); H10W 90/00 (2026.01); H10W 90/792 (2026.01);
Abstract

A semiconductor memory device includes a plurality of transistors arranged in a first direction, and arranged in a second direction and a first wiring layer disposed between a semiconductor substrate and a plurality of voltage supply wirings. Each of the plurality of transistors includes a source region and a drain region. The first wiring layer includes a plurality of first connecting portions disposed at positions overlapping with the plurality of source regions when viewed in a third direction and electrically connected to the plurality of source regions and the plurality of voltage supply wirings, a plurality of second connecting portions disposed at positions overlapping with the plurality of source regions when viewed in the third direction and electrically connected to a plurality of the drain regions and a plurality of conductive layers, and a passing wiring region disposed between a pair of the second connecting portions.


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