Layout for imaging system and pixel cell array with quad row select transistors

Abstract

A pixel cell array includes a plurality of pixel cells, each including one or more photodiodes configured to generate image charge in response to incident light, a floating diffusion coupled to receive the image charge, a source-follower transistor having a gate coupled to the floating diffusion to generate an image signal at a first source/drain region of the source-follower transistor in response to the image charge in the floating diffusion, a first row select transistor having a first source/drain region coupled to the first source/drain region of the source-follower transistor, and a second row select transistor having a first source/drain region coupled to a second source/drain region of the first row select transistor. The first source/drain regions of the second row select transistors included in a first pixel cell and a second pixel cell included in the plurality of pixel cells are coupled together through a common junction.