Phase locked loop circuit and method of operation thereof

Abstract

There is provided a phase locked loop circuit including a phase-frequency detection circuit configured to receive a reference clock signal and a feedback clock signal having a first phase difference from each other, adjust a phase gain based on first phase difference, and generate a first and a second control signals based on the phase gain, a lock detection circuit configured to generate a lock detection signal based on the first phase difference, a charge pump circuit configured to generate a loop filter input signal based on the first and second control signals, a loop filter configured to adjust impedance based on the activated lock detection signal and generate a loop filter output signal based on the adjusted impedance, an oscillator configured to generate a clock signal based on the loop filter output signal, and a divider configured to generate the feedback clock signal by dividing the clock signal.