The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Oct. 31, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Raveesh Magod Ramakrishna, Dallas, TX (US);

Maik Peter Kaufmann, Freising, DE;

Michael Lueders, Freising, DE;

Johan Strydom, Saratoga, CA (US);

Stefan Herzer, Marzling, DE;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01); H03K 5/00 (2006.01); H03K 5/13 (2014.01);
U.S. Cl.
CPC ...
H03K 17/6871 (2013.01); H03K 5/13 (2013.01); H03K 2005/00019 (2013.01);
Abstract

In described examples, an integrated circuit includes first and second current sources, first and second switches, a dV/dt phase detector, a control circuit, and source, gate, and drain terminals for coupling to, respectively, a source, gate, and drain of a power FET. The first switch is coupled between the first current source and the gate terminal. The second switch is coupled between the second current source and the gate terminal. The dV/dt phase detector detects a dV/dt phase of the power FET and outputs to the control circuit. The control circuit controls the first and second switches to perform a turn-on sequence of the power FET, including: closing the first switch while keeping the second switch open; and after receiving a signal from the dV/dt phase detector indicating the dV/dt phase has started, opening the first switch, and closing the second switch.


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