The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Dec. 13, 2024
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Masashi Nakata, Yokohama Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 5/131 (2014.01); G11C 7/22 (2006.01); H03K 3/037 (2006.01); H03K 5/135 (2006.01);
U.S. Cl.
CPC ...
H03K 5/131 (2013.01); G11C 7/222 (2013.01); H03K 3/037 (2013.01); H03K 5/135 (2013.01);
Abstract

According to one embodiment, semiconductor integrated circuit includes: first and second pulse generators that generate first and second pulse signals based on a first signal, and third and fourth pulse signal based on a second signal, respectively; first and second inversion buffers that output a third signal based on inputs of the first and third pulse signals, and a fourth signal based on inputs of the second and fourth pulse signal, respectively; wherein, when a logic level of the first or the third pulse signal changes from a first logic level to a second logic level, the first inversion buffer changes a logic level of the third signal, and when a logic level of the second or the fourth pulse signal changes from the first logic level to the second logic level, the second inversion buffer changes a logic level of the fourth signal.


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