The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Apr. 01, 2025
Applicants:

Hefei Boe Joint Technology Co., Ltd., Hefei, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Xuehuan Feng, Beijing, CN;

Yongqian Li, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3266 (2016.01); G09G 3/3233 (2016.01); H10K 59/131 (2023.01);
U.S. Cl.
CPC ...
G09G 3/3266 (2013.01); G09G 3/3233 (2013.01); H10K 59/131 (2023.02); G09G 2300/0408 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01); G09G 2330/021 (2013.01);
Abstract

Disclosed is a display panel including a base substrate (), and a gate drive circuit (), a plurality of clock signal lines, and a plurality of connecting lines () that are disposed on the base substrate (). The plurality of clock signal lines are located on a side of the gate drive circuit () along a first direction (X) and are arranged in sequence. Each connecting line () is electrically connected with the gate drive circuit () and a clock signal line. At least one connecting line () includes a load adjusting portion () configured to compensate for a load difference between different clock signal lines. An orthographic projection of the load adjusting portion () of the at least one connecting line () on the base substrate () is at least partially overlapped with an orthographic projection of at least one clock signal line on the base substrate ().


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