Simulating quantum computing circuits using sparse state partitioning

Abstract

In various examples, systems and methods for simulating quantum circuits using sparse state partitioning are provided. The quantum state of a quantum circuit may be partitioned into one or more state vector partition candidates that may form sparse state partitions that avoid memory operations for one or more state elements of the quantum circuit's state vector. Gate grouping, gate complexity, and/or qubit ordering optimization algorithms may be applied and the state vector partition candidate evaluated against a computing platform topology profile using a cost evaluation function. The cost evaluation function may estimate an efficiency associated with executing that state vector partition candidate given the processing resources of the currently available simulation platform for running the simulation. A state vector partition candidate optimized for the simulation platform may be passed to the simulation platform as a set of state vector partitions in order to simulate the quantum circuit.