System and method for automatic generation of standard cells using satisfiability modulo theory solver

Abstract

An electronic design automation tool and method of operating the same are provided for placement and routing of intra-cell devices in integrated circuits (ICs). Generally the method includes: receiving inputs, creating an instance of a Satisfiability Modulo Theory (SMT) problem for placement and routing by translating the inputs into a set of SMT constraints relating to the placement of intra-cell transistors and routing for interconnects to intra-cell transistors, calling a SMT solver and using the set of SMT constraints generating a solution to the SMT problem, and if the solution satisfies requirements of the inputs and a predetermined area requirement specified by a user, creating and outputting a layout for placement and routing of intra-cell transistors in the IC. The process may be repeated until a predetermined number of ranked solutions or an optimal solution is found. Other embodiments are also disclosed.