The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Jan. 06, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyunjae Jang, Suwon-si, KR;

Jongwon Kim, Hwaseong-si, KR;

In Huh, Suwon-si, KR;

Satbyul Kim, Seoul, KR;

Younggu Kim, Hwaseong-si, KR;

Yunjun Nam, Suwon-si, KR;

Changwook Jeong, Hwaseong-si, KR;

Moonhyun Cha, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 119/02 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 2119/02 (2020.01);
Abstract

A method for simulating a layout of an integrated circuit manufactured by a semiconductor process includes extracting a plurality of pattern layouts from layout data that defines the layout, generating training data by amplifying the plurality of pattern layouts and at least one parameter provided from the semiconductor process, generating sample data by sampling the training data, generating feature data including a three-dimensional array from the sample data, providing the sample data and the feature data to a simulator and a machine learning model, respectively, and training the machine learning model based on an output of the machine learning model and an output of the simulator.


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