The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Jun. 29, 2023
Applicant:

Lodestar Licensing Group Llc, Evanston, IL (US);

Inventors:

Perry V. Lea, Eagle, ID (US);

Glen E. Hush, Boise, ID (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 11/4076 (2006.01); G11C 11/4091 (2006.01); G11C 11/4093 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); G11C 11/4097 (2006.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/0635 (2013.01); G06F 3/0665 (2013.01); G06F 3/0689 (2013.01); G11C 7/1006 (2013.01); G11C 7/1009 (2013.01); G11C 7/106 (2013.01); G11C 7/222 (2013.01); G11C 11/4076 (2013.01); G11C 11/4091 (2013.01); G11C 11/4093 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 11/4097 (2013.01); G11C 2207/2245 (2013.01);
Abstract

The present disclosure includes apparatuses and methods for simultaneous in data path compute operations. An apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. A plurality of shared I/O lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. The first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period.


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