The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2026
Filed:
Apr. 24, 2024
Applicant:
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Inventor:
Meng-Han Lin, Hsinchu City, TW;
Assignee:
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/285 (2006.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 64/0112 (2026.01); H10D 84/013 (2025.01); H10D 84/0142 (2025.01); H10D 84/0144 (2025.01); H10D 84/0151 (2025.01); H10D 84/0156 (2025.01);
Abstract
A manufacturing method of a semiconductor structure including the following steps is provided. A substrate is provided. A semiconductor layer is formed in the substrate. A portion of the semiconductor layer and a portion of the substrate are removed to form a trench in the substrate. An isolation structure is formed in the trench. After the isolation structure is formed, the semiconductor layer is removed to form a first recess in the substrate. A gate dielectric layer is formed on the substrate exposed by the first recess.