The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

Dec. 14, 2022
Applicant:

Electronics and Telecommunications Research Institute, Daejeon, KR;

Inventors:

Jungwook Lim, Daejeon, KR;

Jieun Kim, Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/69 (2025.01); G06N 3/065 (2023.01); G11C 11/56 (2006.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
H10D 30/691 (2025.01); G06N 3/065 (2023.01); G11C 11/5671 (2013.01); H10D 30/6755 (2025.01);
Abstract

A synaptic element performing a multi-level logic operation includes a gate electrode to which a gate voltage pulse is applied, a first electrode, a second electrode, and a multilayer tunnel insulating film in contact with each of the gate electrode, the first electrode, and the second electrode, and disposed such that the gate electrode is spaced apart from the first electrode and the second electrode, and the synaptic element generates a tunneling current flowing from the first electrode to the gate electrode through the multilayer tunnel insulating film based on the gate voltage pulse, the synaptic element operates in one of a turn-on mode, a turn-off mode, and an intermediate mode different from the turn-on mode and the turn-off mode based on the tunneling current, and the synaptic element is trained to generate a drain current in each of the turn-on mode, the turn-off mode, and the intermediate mode.


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