Nonvolatile memory unit cell and array architecture

Abstract

A non-volatile memory cell structure is designed to enable high density logic-compatible embedded flash memory. The non-volatile memory device includes a substrate including a plurality of n-well, said n-well including a plurality of diffusion regions, said diffusion regions are separated from each other by one or more non-active regions of the substrate; and, a first unit cell comprising: a first memory unit including a first P-MOS transistor formed on a first n-well on the substrate; a second memory unit including a second P-MOS transistor formed on as second n-well on the substrate, wherein the first and second P-MOS transistors overlap at least partially with a second unit cell laterally adjacent to the first unit cell; a third memory unit consisting of three N-MOS transistors formed on the substrate and connected in series and arranged parallel to a width of the unit cell; a first connection line coupling a gate of one of the three N-MOS transistor to a gate of the first P-MOS transistor along a length of the unit cell; and a second connection line coupling a gate of the first P-MOS transistor to a gate of the second P-MOS transistor along the length of the unit cell, wherein the three N-MOS transistors in series consist of a first N-MOS transistor sharing an active region with a second N-MOS transistor, and the second N-MOS transistor sharing an active region with a third N-MOS transistor.